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| HT48R54A I/O Type 8-Bit OTP MCU with 1616 High Current LED Driver Technical Document * Tools Information * FAQs * Application Note - HA0002E HA0007E HA0019E HA0020E HA0075E Reading Larger than Usual MCU Tables Using the MCU Look Up Table Instructions Using the Watchdog Timer in the HT48 MCU Series Using the Timer/Event Counter in the HT48 MCU Series MCU Reset and Oscillator Circuits Application Note Features * Operating voltage: * RC/XTAL and 32768Hz crystal oscillator * Dual clock system offers three operating modes - Normal mode: Both RC/XTAL and 32768Hz clock fSYS=32768Hz: 2.2V~5.5V fSYS=4MHz: 2.2V~5.5V fSYS=8MHz: 3.3V~5.5V * 4k15 program memory ROM * 1928 data memory RAM * 16 bidirectional I/O lines * 24 output lines * One external interrupt input * Two internal interrupt * Two 8 bit programmable timer/event counter * 32768 Real Time Clock function * 6-level subroutine nesting * Watchdog Timer (WDT) * Low voltage reset (LVR) * PFD/Buzzer driver output active - Slow mode: 32768Hz clock only - Idle mode: Periodical wake-up by watchdog timer overflow * HALT function and wake-up feature reduce power consumption * 15-bit table read instructions * 63 powerful instructions * One instruction cycle: 4 system clock periods * All instructions in 1 or 2 instruction cycles * Bit manipulation instructions * Up to 0.5ms instruction cycle with 8MHz system clock * 44/52-pin QFP package General Description This device is an 8-bit high performance, RISC architecture microcontroller specifically designed for multiple I/O control product applications. The advantages of low power consumption, I/O flexibility, timer functions, oscillator options, HALT and wake-up functions, watchdog timer, as well as low cost, enhance the versatility of these devices to suit a wide range of application possibilities such as industrial control, consumer products, subsystem controllers, etc. Rev. 1.00 1 July 27, 2007 HT48R54A Block Diagram T1S In te rru p t C ir c u it S ta c k P ro g ra m C o u n te r S ta c k P o in te r IN T C M TM R1C TM R1 M U X U X RTC OSC fS YS P A 3 /T M R 1 A d d re s s D e c o d e r P ro g ra m M e m o ry L o o k u p T a b le P o in te r L o o k u p T a b le R e g is te r WDT C o u n te r M U X fS Y S /4 RTC OSC W DT OSC TM R0 TM R0C M U M X U P r e s c a le r X fS YS /4 In s tr u c tio n R e g is te r MUX ACC PAC ALU PORT A P A 0 /B Z P A 1 /B Z PA M e m o ry P o in te r MUX P A 2 /T M R 0 P A 3 /T M R 1 PA4~PA6 P A 7 /P F D PBC PB PORT B PB0~PB7 In s tr u c tio n D ecoder S h ifte r T im in g G e n e ra to r A d d re s s D e c o d e r P ro g ra m M e m o ry W DT O s c illa to r PC PORT C PC 0~PC 7 R C o r C ry s ta l O s c illa to r RTC O s c illa to r R eset& LVR PD PORT D PORT E P D 0 /IN T PD 1~PD 7 OSC1 OSC2 OSC3 OSC4 RE VDD VSS V S,V B,V ,V SS DD DDC SSD E PE PE0~PE7 Rev. 1.00 2 July 27, 2007 HT48R54A Pin Assignment PA PA P A 2 /T P A 3 /T PA PA P A 2 /T P A 3 /T Z Z 3 2 1 4 0 4 44 43 42 41 40 39 38 37 36 35 34 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 O SC SC VD SC SC RE 0 /B 1 /B MR MR PA PA PA O O O O O O D O SC SC VD SC SC RE 0 /B 1 /B MR MR PA S 1 VS PB PB PB PB VD VD PB PB PB PB 0 S 7 6 5 4 3 2 1 P A 7 /P F PE PE PE VSS PE PE PE PE PE P D 0 /IN PD PD D 2 E 5 6 7 T 1 2 4 3 6 7 9 10 11 12 13 8 1 0 2 3 4 5 1 D S Z Z 52515049484746454443424140 6 5 4 1 0 1 39 38 37 36 35 H T48R 54A 5 2 Q F P -A 34 33 32 31 30 29 28 27 VS PB PB PB PB VD VD PB PB PB PB PC PC 0 S 7 6 5 4 3 2 1 2 4 3 PA PA P A 7 /P F PE PE PE VSS PE PE PE PE D 6 1 2 E 5 6 4 3 0 5 33 32 31 30 H T48R 54A 4 4 Q F P -A 29 28 27 26 25 24 23 DB DB DB DB 7 6 14151617181920212223242526 Pin Description Pin Name I/O Options Description Bidirectional 8-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. A pull-high resistor can be connected via configuration option. Each pin can be setup to be a wake-up input via configuration options. The PA0 and PA1 are pin-shared with the BZ and BZ, respectively. The timer input TMR0 is pin-shared with PA2. The timer input TMR1 is pin-shared with PA3. The PFD function is pin-shared with PA7 which is determined by configuration option. Bidirectional 8-bit input/output port. When used as output port, they are configured as PMOS output pins. PC0~PC7 are PMOS output pins. External interrupt input. Pin-shared with PD0 and activated on a high to low or low to high transition. PD0 is NMOS type output pin. PD1~PD7 are NMOS output pins. PE0~PE7 are NMOS output pins. Schmitt trigger reset input. Active low. OSC1 and OSC2 are connected to an RC network or a crystal (by options) for the internal system clock. In the case of RC operation, OSC2 is the output terminal for 1/4 system clock. Real time clock oscillator. OSC3 and OSC4 are connected to a 32768Hz crystal oscillator for system clock timing purposes. Positive power supply PB port positive power supply PC port positive power supply Negative Power supply, ground PD & PE port negative power supply, ground PC PC PC PC VD PC PC PC PC VS PD 7 6 5 4 DC 3 2 1 0 SD 0 /IN T PC5 PC4 VDDC PC3 PC2 PC1 PC0 PD7 PD6 PD5 VSSD PD4 PD3 PA0/BZ PA1/BZ PA2/TMR0 PA3/TMR1 PA4~PA6 PA7/PFD I/O Pull-high Wake-up Buzzer PFD PB0~PB7 PC0~PC7 PD0/INT PD1~PD7 PE0~PE7 RES OSC1 OSC2 OSC3 OSC4 VDD VDDB VDDC VSS VSSD, VSSE I/O O I/O O O I I O I O 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 RC or Crystal 3/4 3/4 3/4 3/4 3/4 3/4 Rev. 1.00 3 July 27, 2007 HT48R54A Absolute Maximum Ratings Supply Voltage ...........................VSS-0.3V to VSS+6.0V Input Voltage..............................VSS-0.3V to VDD+0.3V IOL Total ..............................................................300mA Total Power Dissipation .....................................500mW Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Storage Temperature ............................-50C to 125C Operating Temperature...........................-40C to 85C IOH Total............................................................-200mA D.C. Characteristics Symbol Parameter Test Conditions VDD 3/4 VDD Operating Voltage 3/4 3/4 IDD1 Operating Current (Crystal OSC, RC OSC) Operating Current (Crystal OSC, RC OSC) Operating Current (*RTC OSC Enabled, Crystal OSC Disabled, RC OSC Disabled) Standby Current (WDT OSC, *RTC OSC Enabled) Standby Current (WDT OSC Disabled, *RTC OSC Enabled) Standby Current (WDT OSC Enabled, RTC OSC Disabled) Standby Current (WDT OSC, RTC OSC Disabled) Input Low Voltage for I/O Ports Input High Voltage for I/O Ports Input Low Voltage (RES) Input High Voltage (RES) 3V 5V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3/4 3/4 3/4 3/4 No load, fSYS=8MHz No load, fSYS=32768Hz No load, system HALT No load, system HALT No load, system HALT No load, system HALT 3/4 3/4 3/4 3/4 2.1V option VLVR Low Voltage Reset 3/4 3.15V option 4.2V option IOL1 3V I/O Port Sink Current for PA 5V IOL2 3V I/O Port Sink Current for PD, PE 5V VOL=0.1VDD VOL=0.1VDD Conditions fSYS=4MHz fSYS=8MHz fSYS=32768Hz No load, fSYS=4MHz Min. 2.2 3.3 2.2 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 0 0.7VDD 0 0.9VDD 1.98 2.98 3.98 4 10 8 20 Typ. 3/4 3/4 3/4 1.2 2.5 4 20 50 3 6 1 2 2 4 3/4 3/4 3/4 3/4 3/4 3/4 2.1 3.15 4.2 8 20 16 40 Max. 5.5 5.5 5.5 2 Ta=25C Unit V mA 5 8 40 100 5 10 2 4 4 8 1 2 0.3VDD VDD 0.4VDD VDD 2.22 3.32 4.42 3/4 3/4 3/4 3/4 mA mA IDD2 IDD3 ISTB1 mA ISTB2 mA ISTB3 mA ISTB4 VIL1 VIH1 VIL2 VIH2 mA V V V V V V V mA mA Rev. 1.00 4 July 27, 2007 HT48R54A Symbol Parameter Test Conditions VDD 3V I/O Port Source Current for PA 5V IOH2 3V I/O Port Source Current for PB, PC 5V RPH 3V Pull-high Resistance 5V 3/4 VOH=0.9VDD Conditions VOH=0.9VDD Min. -2 -5 -4 -10 20 10 Typ. -4 -10 -8 -20 60 30 Max. 3/4 3/4 3/4 3/4 100 50 kW Unit IOH1 mA mA Note: * RTC OSC in slow start oscillating A.C. Characteristics Symbol Parameter System Clock (Crystal OSC, RC OSC) Timer I/P Frequency Test Conditions VDD 3/4 3/4 3/4 3/4 3V 5V tFSP1 tFSP2 tRES tSST tLVR tINT Note: fSP Time-out Period Clock Source from WDT fSP Time-out Period Clock Source from RTC Oscillator External Reset Low Pulse Width System Start-up Timer Period Low Voltage Width to Reset Interrupt Pulse Width tSYS=1/fSYS *tRTC@30.5ms 3/4 3/4 3/4 3/4 3/4 3/4 Conditions 2.2V~5.5V 3.3V~5.5V 2.2V~5.5V 3.3V~5.5V 3/4 3/4 With prescaler (fS/4096) With prescaler (fS/4096) 3/4 Power-up or wake-up from HALT 3/4 3/4 Min. 400 400 0 0 45 32 3/4 3/4 1 3/4 0.25 1 Typ. 3/4 3/4 3/4 3/4 90 65 221 221 3/4 1024 1 3/4 Max. 4000 Ta=25C Unit fSYS kHz 8000 4000 kHz 8000 180 130 3/4 3/4 3/4 3/4 2 3/4 ms ms tWDTOSC *tRTC ms tSYS ms ms fTIMER tWDTOSC Watchdog Oscillator Period Rev. 1.00 5 July 27, 2007 HT48R54A Functional Description Execution Flow The system clock for the microcontroller is derived from a crystal oscillator or an RC oscillator or a RTC oscillator. The system clock is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruction to be effectively executed in a cycle. If an instruction changes the program counter, two cycles are required to complete the instruction. Program Counter - PC The program counter (PC) controls the sequence in which the instructions stored in the program ROM are executed and its contents specify a full range of program memory. After accessing a program memory word to fetch an instruction code, the contents of the program counter are T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4 incremented by one. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call or return from subroutine, initial reset, internal interrupt, external interrupt or return from interrupt, the PC manipulates the program transfer by loading the address corresponding to each instruction. The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise proceed with the next instruction. The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the PCL performs a short jump. The destination will be within 256 locations. When a control transfer takes place, an additional dummy cycle is required. S y s te m O S C 2 (R C C lo c k o n ly ) PC PC PC+1 PC+2 F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 ) F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C ) F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 ) Execution Flow Program Counter *11 0 0 0 0 *10 0 0 0 0 *9 0 0 0 0 *8 0 0 0 0 *7 0 0 0 0 *6 0 0 0 0 *5 0 0 0 0 *4 0 0 0 0 *3 0 0 1 1 *2 0 1 0 1 *1 0 0 0 0 *0 0 0 0 0 Mode Initial Reset External Interrupt Timer/Event Counter 0 Overflow Timer/Event Counter 1 Overflow Skip Loading PCL Jump, Call Branch Return from Subroutine Program Counter+2 *11 #11 S11 *10 #10 S10 *9 #9 S9 *8 #8 S8 @7 #7 S7 @6 #6 S6 @5 #5 S5 @4 #4 S4 @3 #3 S3 @2 #2 S2 @1 #1 S1 @0 #0 S0 Program Counter Note: *11~*0: Program counter bits #11~#0: Instruction code bits S11~S0: Stack register bits @7~@0: PCL bits Rev. 1.00 6 July 27, 2007 HT48R54A Program Memory - ROM The program memory is used to store the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 409615 bits, addressed by the program counter and table pointer. Certain locations in the program memory are reserved for special usage: * Location 000H This area is reserved for program initialisation. After a chip reset, the program always begins execution at location 000H. * Location 004H TBLH is read only and cannot be restored. If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be changed by the table read instruction used in the ISR, therefore errors may occur. In other words, using the table read instruction in the main routine and the ISR simultaneously should be avoided. However, if the table read instruction has to be applied in both the main routine and the ISR, the interrupt should be disabled prior to using the table read instruction. It should not be enabled until the TBLH has been backed up. All table related instructions require two cycles to complete the operation. These areas may function as normal program memory depending upon the requirements. 000H 004H 008H 00CH n00H nFFH L o o k - u p T a b le ( 2 5 6 w o r d s ) D e v ic e In itia liz a tio n P r o g r a m E x te r n a l In te r r u p t S u b r o u tin e T im e r /E v e n t C o u n te r 0 In te r r u p t S u b r o u tin e T im e r /E v e n t C o u n te r 1 In te r r u p t S u b r o u tin e P ro g ra m M e m o ry This area is reserved for the external interrupt service program. If the INT input pin is activated, the interrupt is enabled and the stack is not full, the program begins execution at location 004H. * Location 008H This area is reserved for the timer/event counter 0 interrupt service program. If a timer interrupt results from a timer/event counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 008H. * Location 00CH This area is reserved for the timer/event counter 1 interrupt service program. If a timer interrupt results from a timer/event counter 1 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 00CH. * Table location F00H FFFH L o o k - u p T a b le ( 2 5 6 w o r d s ) 1 5 b its N o te : n ra n g e s fro m 0 to 7 Program Memory Stack Register - STACK This is a special part of the memory which is used to save the contents of the program counter only. The stack is organized into 6 levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the stack pointer (SP) and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the program counter is restored to its previous value from the stack. After a chip reset, the stack pointer will point to the top of the stack. Table Location Any location in the program memory space can be used as look-up tables. The instructions TABRDC [m] (the current page, one page=256 words) and TABRDL [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H). Only the destination of the lower-order byte in the table is well-defined, the other bits of the table word are transferred to the lower portion of the TBLH, and the remaining 2-bit words are read as 0. The Table Higher-order byte register (TBLH) is read only. The table pointer (TBLP) is a read/write register (07H), which indicates the table location. Before accessing the table, the location must be placed in the TBLP. The Instruction TABRDC [m] TABRDL [m] *11 P11 1 *10 P10 1 *9 P9 1 *8 P8 1 *7 @7 @7 *6 @6 @6 *5 @5 @5 *4 @4 @4 *3 @3 @3 *2 @2 @2 *1 @1 @1 *0 @0 @0 Table Location Note: *11~*0: Table location bits @7~@0: Table pointer bits Rev. 1.00 7 July 27, 2007 P11~P8: Current program counter bits HT48R54A If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the stack pointer is decremented, by RET or RET, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. In a similar case, if the stack is full and a CALL is subsequently executed, a stack overflow occurs and the first entry will be lost. Only the most recent 6 return addresses are stored. Data Memory - RAM The data memory is divided into two functional groups, namely, function registers and general purpose data memory (1928). Most are read/write, but some are read only. All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and reset by SET [m].i and CLR [m].i. They are also indirectly accessible through the memory pointer registers. Indirect Addressing Register Location 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write operation of [00H] ([02H]) will access the data memory pointed to by MP0 (MP1). Reading location 00H (02H) itself indirectly will return the result 00H. Writing indirectly results in no operation. The memory pointer registers, MP0 and MP1, are 8-bit registers. Accumulator The accumulator is closely related to ALU operations. It is also mapped to location 05H of the data memory and can carry out immediate data operations. The data movement between two data memory locations must pass through the accumulator. Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic operations. The ALU provides the following functions: * Arithmetic operations (ADD, ADC, SUB, SBC, DAA) * Logic operations (AND, OR, XOR, CPL) * Rotation (RL, RR, RLC, RRC) * Increment and Decrement (INC, DEC) * Branch decision (SZ, SNZ, SIZ, SDZ ....) 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H IA R 0 MP0 IA R 1 MP1 ACC PCL TBLP TBLH STATUS IN T C TM R0 TM R 0C TM R1 TM R 1C PA PAC PB PBC PC PD PE S p e c ia l P u r p o s e D a ta M e m o ry MODE 40H FFH G e n e ra l P u rp o s e D a ta M e m o ry (1 9 2 B y te s ) :U nused R e a d a s "0 0 " RAM Mapping (TO). It also records the status information and controls the operation sequence. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results from those intended. The TO flag can be affected only by a system power-up, a WDT time-out or executing the CLR WDT or HALT instruction. The PDF flag can be affected only by executing the HALT or CLR WDT instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. 8 July 27, 2007 The ALU not only saves the results of a data operation but also changes the status register. Status Register - STATUS This 8-bit register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag Rev. 1.00 HT48R54A Bit No. 0 Label C Function C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation, otherwise C is cleared. C is also affected by a rotate through carry instruction. AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction, otherwise AC is cleared. Z is set if the result of an arithmetic or logic operation is zero, otherwise Z is cleared. OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa, otherwise OV is cleared. PDF is cleared by system power-up or executing the CLR WDT instruction. PDF is set by executing the HALT instruction. TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. Unused bit, read as 0 STATUS (0AH) Register In addition, on entering the interrupt sequence or executing the subroutine call, the status register will not be automatically pushed onto the stack. If the contents of the status register are important and if the subroutine can corrupt the status register, precautions must be taken to save it properly. Interrupt The device provides an external interrupt and internal timer/event counter interrupt. The Interrupt Control Register (INTC;0BH) contains the interrupt control bits to set the enable or disable bits and the interrupt request flags. Once an interrupt subroutine is serviced, all the other interrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may occur during this interval but only the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the EMI bit and the corresponding bit of the INTC may be set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must be prevented from becoming full. Bit No. 0 1 2 3 4 5 6 7 Label EMI EEI ET0I ET1I EIF T0F T1F 3/4 All interrupts have a wake-up capability. When an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at specified location in the program memory. Only the program counter is pushed onto the stack. If the contents of the register or status register are altered by the interrupt service program, an action which may corrupt the desired control sequence, the contents should be saved in advance. An external interrupt is triggered either on a high to low or low to high transition on the INT pin. The related interrupt request flag, EIF; bit 4 of the INTC register will then be set. When the interrupt is enabled, the stack is not full and the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag (EIF) and EMI bits will be cleared to disable other interrupts. The internal timer/event counter 0 interrupt is initialised by setting the timer/event counter 0 interrupt request flag, T0F; bit 5 of the INTC register. This will be caused by a timer 0 overflow. When the interrupt is enabled, the stack is not full and the T0F bit is set, a subroutine call to location 08H will occur. The related interrupt request flag, T0F, will then be reset and the EMI bit cleared to disable further interrupts. Function Controls the master (global) interrupt (1=enable; 0=disable) Controls the external interrupt (1=enable; 0=disable) Controls the Timer/Event Counter 0 interrupt (1=enable; 0=disable) Controls the Timer/Event Counter 0 interrupt (1=enable; 0=disable) External interrupt request flag (1=active; 0=inactive) Internal Timer/Event Counter 0 request flag (1=active; 0=inactive) Internal Timer/Event Counter 1 request flag (1=active; 0=inactive) Unused bit, read as 0 INTC (0BH) Register Rev. 1.00 9 July 27, 2007 1 2 3 4 5 6, 7 AC Z OV PDF TO 3/4 HT48R54A The internal timer/event counter 1 interrupt is initialised by setting the timer/event counter 1 interrupt request flag, T1F; bit 6 of the INTC register. This will be caused by a timer 1 overflow. When the interrupt is enabled, the stack is not full and the T1F bit is set, a subroutine call to location 0CH will occur. The related interrupt request flag, T1F, will then be reset and the EMI bit cleared to disable further interrupts. During the execution of an interrupt subroutine, other interrupt acknowledge signals are held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are set to 1, if the stack is not full. To return from the interrupt subroutine, a RET or RETI instruction may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not. Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests the following table shows the priority that is applied. These can be masked by resetting the EMI bit. Interrupt Source External Interrupt Timer/Event Counter 0 Overflow Timer/Event Counter 1 Overflow Priority 1 2 3 Vector 04H 08H 0CH It is recommended that a program does not use the CALL subroutine within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and enabling the interrupt is not well controlled, the original control sequence will be damaged if a CALL is executed in the interrupt subroutine. Oscillator Configuration These devices provide three types of system oscillator circuits, an crystal oscillator, an RC oscillator and a 32768Hz crystal oscillator, the choice crystal or RC oscillator is determined by configuration option. If an RC oscillator is used, an external resistor, whose resistance must range from 130kW to 2.5MW, should be connected between OSC1 and VSS. The RC oscillator provides the most cost effective solution, however, the frequency of oscillation may vary with VDD, temperatures and the chip itself due to process variations. It is, therefore, not suitable for timing sensitive operations where an accurate oscillator frequency is desired. The other oscillator circuit is designed for the real time clock. For this device, only a 32768Hz crystal oscillator can be used. The crystal should be connected between OSC3 and OSC4. The RTC oscillator circuit can be controlled to start up quickly by setting the QOSC bit (bit 4 of mode). It is recommended to turn on the quick oscillating function at power on until the RTC oscillator is stable, and then turn it off after 2 seconds to reduce power consumption. The WDT oscillator is a free running on-chip RC oscillator, and requires no external components. Although when the system enters the power down mode, the system clock stops, the WDT oscillator will keep running with a period of approximately 65ms at 5V. The WDT oscillator can be disabled by a configuration option to conserve power. The timer/event counter 0 interrupt request flag (T0F), The timer/event counter 1 interrupt request flag (T1F), external interrupt request flag (EIF); enable timer/event counter 0 interrupt bit (ET0I), enable timer/event counter 1 interrupt bit (ET1I), enable external interrupt bit (EEI), enable master interrupt bit (EMI) constitute an interrupt control register (INTC) which is located at 0BH in the data memory. EMI, EEI, ET0I, ET1I are used to control the enabling/disabling of interrupts. These bits prevent the requested interrupt from being serviced. Once the interrupt request flags, T0F, T1F and EIF, are set, they will remain in the INTC register until the interrupts are serviced or cleared by a software instruction. V 470pF DD OSC1 R OSC 10pF OSC3 OSC1 fS YS /4 RC OSC2 O s c illa to r OSC4 32768H z C r y s ta l O s c illa to r OSC2 C r y s ta l O s c illa to r System Oscillator Rev. 1.00 10 July 27, 2007 HT48R54A Watchdog Timer - WDT The WDT clock source is implemented by a internal WDT OSC, the external 32768Hz (fRTC) or the instruction clock (system clock divided by 4), the choice of which is determined by configuration option. This timer is designed to prevent software malfunctions or sequences jumping to an unknown location with unpredictable results. The Watchdog can be disabled by a configuration option. If the Watchdog Timer is disabled, all the executions related to WDT will result in no operation. If the device operates in a noisy environment, using the on-chip WDT OSC or 32768Hz crystal oscillator is strongly recommended. When the WDT clock source is selected, it will be first divided by 16 (4-stage), and then divided by the TMR0C prescaler (8-stage), after that, divided by 512 (9-stage) to get the nominal time-out period. By using the TMR0C prescaler, longer time-out periods can be realized. Writing data to PSC2, PSC1, PSC0 can give different time-out periods. The WDT OSC period is 65ms. This time-out period may vary with temperature, VDD and process variations. The WDT OSC keep running in any operation mode. If the instruction clock (system clock/4) is selected as the WDT clock source, the WDT operates in the same manner. If the WDT clock source is the 32768Hz, the WDT also operates in the same manner. The WDT time-out under normal mode or slow mode will initialize a chip reset and set the status bit TO. But in the idle mode, that is after a HALT instruction is executed, the time-out will initialize a warm reset and only the program counter and stack pointer are reset to 0. To clear the WDT contents (not including the 4-bit divider and the 8-stage prescaler), three methods are adopted; an external reset (a low level to RES pin), software instruction and a HALT instruction. The software instruction includes a CLR WDT instruction, and the instruction pair CLR WDT1 and CLR WDT2. Of these two types of instruction, only one can be active depending on the configuration option WDT instruction. If the CLR WDT is selected (i.e. One clear instruction), any execution of the CLR WDT instruction will clear the WDT. In the case that CLR WDT1 and CLR WDT2 are chosen (i.e. two clear instructions), these two instructions must be executed to clear the WDT; otherwise, the WDT may reset the chip as a result of a time-out. Operation Mode The device support two system clocks and three operation modes. The system clock can be either an RC/XTAL oscillator or a 32768Hz RTC. The three operational modes are, Normal, Slow, or Idle mode. These are all selected by software. S y s te m C lo c k /4 32768H z O p tio n S e le c t fS 4 - B it D iv id e r 8 - S ta g e P r e s c a le r W DT OSC PSC2~PSC0 8 -to -1 M U X 9 - B it C o u n te r W D T T im e - o u t Watchdog Timer Bit No. Label Function System clock high/low mode select bit 0= RC/XTAL system clock select 1= 32768Hz system clock select and RC/XTAL system clock stop Note that if the 32768Hz system clock is selected, then the WDT clock source configuration option must also select the 32768Hz oscillator as its clock source, otherwise unpredictable system operation may occur. Unused bit, read as 0 32768Hz OSC quick start-up 0=quick start; 1=slow start Unused bit, read as 0 MODE (20H) Register 0 MODS 1, 2, 3 4 5, 6, 7 3/4 QOSC 3/4 Rev. 1.00 11 July 27, 2007 HT48R54A Mode Normal Slow Idle System Clock RC/XTAL oscillator 32768Hz HALT HALT Instruction No Executed No Executed Be executed Operation Mode Power Down Operation - HALT The HALT mode is entered using the HALT instruction and results in the following: * The system oscillator will be turned off but the WDT MODS 0 1 x RC Oscillator On Off Off 32768Hz On On On The RTC oscillator will keep running when the device is in the HALT mode, if the RTC oscillator is enabled. Reset There are three ways in which a reset can occur: * RES reset during normal operation * RES reset during HALT * WDT time-out reset during normal operation remains operational if its clock source is the internal WDT oscillator. * The contents of the on chip RAM and registers remain unchanged. * The WDT will be cleared. The WDT will resume count- ing, if the WDT clock souce is the internal WDT oscillator. * All of the I/O ports will maintain their original status. * The PDF flag will be set and the TO flag will be cleared. The system can leave the HALT mode by means of an external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset causes a device initialization and the WDT overflow performs a warm reset. After the TO and PDF flags are examined, the reason behind the reset can be determined. The PDF flag is cleared by a system power-up or executing the CLR WDT instruction and is set when executing the HALT instruction. The TO flag is set if the WDT time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other circuits remain in their original status. The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each port A pin can be independently selected to wake up the device via configuration options. If awakened by an I/O port stimulus, the program will resume execution at the next instruction. If awakened by an interrupt, two sequences may occur. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. If the interrupt is enabled and the stack is not full, the regular interrupt response takes place. If an interrupt request flag is set to 1 before entering the HALT mode, the wake-up function of the related interrupt will be disabled. Once a wake-up event occurs, it takes 1024 system clock periods to resume normal operation. In other words, a dummy period will be inserted after a wake-up. If the wake-up results from an interrupt acknowledge signal, the actual interrupt subroutine execution will be delayed by one or more cycles. If the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is finished. To minimize power consumption, all the I/O pins should be carefully managed before entering the HALT status. Rev. 1.00 12 A the time-out during a HALT is different from the other chip reset conditions, since it can perform a warm re set that resets only the program counter and SP, leaving the other circuits in their original state. Some registers remain unchanged during other reset conditions. Most registers are reset to their initial condition when the reset conditions are met. By examining the PDF and TO flags, the program can distinguish between different chip resets. TO PDF 0 u 0 1 1 0 u 1 u 1 RESET Conditions RES reset during power-up RES reset during normal operation RES wake-up HALT WDT time-out during normal operation WDT wake-up HALT Note: u stands for unchanged VDD RES S S T T im e - o u t C h ip R eset tS ST Reset Timing Chart HALT W DT RES W a rm R eset OSC1 SST 1 0 - b it R ip p le C o u n te r S y s te m R eset C o ld R eset Reset Configuration July 27, 2007 HT48R54A To guarantee that the system oscillator is running and stable, the SST (System Start-up Timer) provides an extra delay of 1024 system clock pulses when the system reset (power-up, WDT time-out or RES reset) or when the system awakes from the HALT state. When a system reset occurs, the SST delay is added during the reset period. Any wake-up from HALT will enable the SST delay. An extra option load time delay is added during a system reset (power-up, WDT time-out at normal mode or RES reset). The functional unit chip reset status are shown below. Program Counter Interrupt Prescaler WDT 000H Disable Clear Clear. After master reset, WDT begins counting V DD V DD 0 .0 1 m F 100kW RES 0 .1 m F B a s ic Reset C ir c u it 10kW 0 .1 m F 100kW RES H i-n o is e Reset C ir c u it Reset Circuit Note: Most applications can use the Basic Reset Circuit as shown, however for applications with extensive noise, it is recommended to use the Hi-noise Reset Circuit. Timer/Event Counter Off Input/Output Ports Stack Pointer Input mode Points to the top of the stack The states of the registers are summarised in the table. Register MP0 MP1 ACC PCL TBLP TBLH STATUS INTC TMR0 TMR0C TMR1 TMR1C PA PAC PB PBC PC PD PE MODE Note: Reset (Power On) xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 xxxx xxxx --xx xxxx --00 xxxx --00 -000 xxxx xxxx 00-0 1000 xxxx xxxx 0000 1000 1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 ---0 ---0 * stands for warm reset u stands for unchanged x stands for unknown 13 July 27, 2007 WDT Time-out (Normal Operation) uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu --uu uuuu --1u uuuu --00 -000 xxxx xxxx 00-0 1000 xxxx xxxx 0000 1000 1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 ---0 ---0 RES Reset (Normal Operation) uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu --uu uuuu --uu uuuu --00 -000 xxxx xxxx 00-0 1000 xxxx xxxx 0000 1000 1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 ---0 ---0 RES Reset (HALT) uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu --uu uuuu --01 uuuu --00 -000 xxxx xxxx 00-0 1000 xxxx xxxx 0000 1000 1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 ---0 ---0 WDT Time-out (HALT)* uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu --uu uuuu --11 uuuu --uu -uuu uuuu uuuu uu-u uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---u ---u Rev. 1.00 HT48R54A Timer/Event Counter 0 Two Timer/event counters are implemented in the microcontroller. The timer/event counter 0 contains an 8-bit programmable count-up counter whose clock may be sourced from an external source or from the system clock/4 or fSP. The fSP clock source is implemented by the WDT OSC, an external 32768Hz (fRTC) or an instruction clock (system clock divided by 4), determined by configuration option. If one of these three source is selected, it will be first divided by 16 (4-stage), and then divided by the TMR0C prescaler (8-stage) to get an fSP output period. By using the TMR0C prescaler, longer time-out periods can be realized. Writing data to P0SC2, P0SC1, P0SC0 can give different fSP output periods. Using internal clock sources, there are 2 reference time-bases for the timer/event counter 0. The internal clock source can be sourced from fSYS/4 or fSP via a configuration options. Using an external clock input allows the user to count external events, measure time intervals or pulse widths, or generate an accurate time base, while using the internal clock allows the user to generate an accurate time base. There are two registers related to the timer/event counter 0; TMR0 ([0DH]) and TMR0C ([0EH]). Writing to TMR0 places the start value in the timer/event counter 0 preload register while reading the TMR0 register retrieves the contents of the timer/event counter 0. The TMR0C register is a timer/event counter 0 control register which defines some options. The T0M0, T0M1 bits define the operating mode. The event count mode is used to count external events, which means the clock source must comes from the external timer pin, TMR0. The timer mode functions as a normal timer with the clock source coming from the fINT clock. The pulse width measurement mode can be used to count the duration of a high or low-level signal on the external timer pin, TMR0. The counting is based on the fINT clock. In the event count or timer mode, once the timer/event counter 0 is enabled, it begins counting form the value placed in the timer/event counter 0. From this initial value it will count up to a value of FFH. Once an overflow fS Y S /4 RTC OSC W DT OSC M U X fS fS /1 6 (1 /2 ~ 1 /2 5 6 ) 8 - s ta g e P r e s c a le r 8 -1 M U X P0SC2~P0SC0 fS /4 M P occurs, the counter is reloaded from the timer/event counter 0 preload register and at the same time generates the interrupt request flag, T0F; bit 5 of the INTC. In the pulse width measurement mode with the T0ON and T0E bits equal to one, once it goes from low to high (or high to low if the T0E bits is 0) it will start counting until the TMR0 returns to the original level and resets the T0ON. The measured result will remain in the timer/event counter 0 even if the activated transient occurs again. In other words, only one cycle measurement can be done. Until setting the T0ON, the cycle measurement will function again as long as it receives further transient pulse. Note that, in this operating mode, the timer/event counter 0 starts counting not according to the logic level but according to the transient edges. In the case of counter overflows, the counter is reloaded from the timer/event counter 0 preload register and issues the interrupt request just like the other two modes. To enable the counting operation, the timer 0 ON bit (T0ON; bit 4 of the TMR0C) should be set to 1. In the pulse width measurement mode, the T0ON will be cleared automatically after the measurement cycle is completed. But in the other two modes the T0ON can only be reset by instructions. The overflow of the timer/event counter 0 is one of the wake-up sources. No matter what the operation mode is, writing a 0 to ET0I can disable the corresponding interrupt services. In the case of timer/event counter 0 OFF condition, writing data to the timer/event counter 0 preload register will also reload that data to the timer/event counter 0. But if the timer/event counter 0 is turned on, data written to it will only be kept in the timer/event counter 0 preload register. The timer/event counter 0 will still operate until overflow occurs (a timer/event counter 0 reloading will occur at the same time). When the timer/event counter 0 (reading TMR0) is read, the clock will be blocked to avoid errors. As clock blocking may result in a counting error, this must be taken into consideration by the programmer. The bit2~bit0 of the TMR0C can be used to define the pre-scaling stages of the internal clock sources of the timer/event counter 0. The definitions are as shown. 9 - B it C o u n te r U X T0M 1 T0M 0 f IN T 4 - b it D iv id e r YS W D T T im e - o u t D a ta B u s fS C o n fig u r a tio n O p tio n TM R0 C o n fig u r a tio n O p tio n 8 - B it T im e r /E v e n t C o u n te r 0 P r e lo a d R e g is te r R e lo a d T0E T0M 1 T0M 0 T0O N P u ls e W id th M e a s u re m e n t M o d e C o n tro l 8 - B it T im e r /E v e n t C o u n te r 0 (T M R 0 ) O v e r flo w to In te rru p t Timer/Event Counter 0 Rev. 1.00 14 July 27, 2007 HT48R54A Bit No. Label Function Define the prescaler stages, P0SC2, P0SC1, P0SC0= 000: fSP=fS/32 001: fSP=fS/64 010: fSP=fS/128 011: fSP=fS/256 100: fSP=fS/512 101: fSP=fS/1024 110: fSP=fS/2048 111: fSP=fS/4096 Defines the TMR0 active edge of the timer/event counter: In Event Counter Mode (T0M1,T0M0)=(0,1): 1:count on falling edge; 0:count on rising edge In Pulse Width measurement mode (T0M1,T0M0)=(1,1): 1: start counting on the rising edge, stop on the falling edge; 0: start counting on the falling edge, stop on the rising edge To enable or disable timer 0 counting (0=disable; 1=enable) Unused bit, read as 0 Define the operating mode, T0M1, T0M0= 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMR0C (0EH) Register Timer/Event Counter 1 Using the internal clock sources, there are 2 reference time-bases for timer/event counter 1. The internal clock source can be selected as coming from fSYS or fRTC (selected by T1S bit). The external clock input allows the user to count external events, measure time intervals or pulse widths, or to generate an accurate time base and PFD signals. There are 2 registers related to timer/event counter 1; TMR1(10H), TMR1C(11H). In timer/event counter 1 counting mode (T1ON=1), writing TMR1 will only put the written data to pre-load register (8 bits). The timer/event counter 1 pre-load register is changed by each writing TMR1 operations. Reading TMR1 will also latch the TMR1 to the destination. The TMR1C is the timer/event counter 1 control register, which defines the operating mode, counting enable or disable and active edge. The T1M0, T1M1 bits define the operating mode. The event count mode is used to count external events, which means the clock source comes from an external (TMR1) pin. The timer mode functions as a normal timer with the clock source coming from the fINT1 clock. The pulse width measurement mode can be used to count the high or low level duration of the external signal (TMR1). The counting is based on the fINT1 clock. In the event count or timer mode, once the timer/event counter 1 starts counting, it will count from the current contents in the timer/event counter 1 to FFH. Once overflow occurs, the counter is reloaded from the timer/event counter 1 preload register and generates the corresponding interrupt request flag (T1F; bit 6 of INTC) at the same time. In pulse width measurement mode with the T1ON and T1E bits are equal to one, once the TMR1 has received a transition from low to high (or high to low if the T1E bit is 0) it will start counting until the TMR1 returns to the original level and reset the T1ON. The measured result will remain in the timer/event counter 1 even if the activated transition occurs again. In other words, only one cycle measurement can be done. Until setting the T1ON, the cycle measurement will function again as long as it receives further transition pulse. Note that, in this operating mode, the timer/event counter 1 starts counting not according to the logic level but according to the transition edges. In the case of counter overflows, the counter 1 is reloaded from the timer/event counter 1 pre-load register and issues the interrupt request just like the other two modes. To enable the counting operation, the timer ON bit(T1ON; bit 4 of TMR1C) should be set to 1. In the pulse width measurement mode, the T1ON will be cleared automatically after the measurement cycle is complete. But in the other two modes the T1ON can only be reset by instructions. The overflow of the timer/event counter 1 is one of the wake-up sources. No matter what the operation mode is, writing a 0 to ET1I can disabled the corresponding interrupt service. 15 July 27, 2007 0 1 2 P0SC0 P0SC1 P0SC2 3 T0E 4 5 T0ON 3/4 6 7 T0M0 T0M1 Rev. 1.00 HT48R54A In the case of timer/event counter 1 OFF condition, writing data to the timer/event counter 1 pre-load register will also load the data to timer/event counter 1. But if the timer/event counter 1 is turned on, data written to the timer/event counter 1 will only be kept in the timer/event counter 1 pre-load register. The timer/event counter 1 will still operate until the overflow occurs (a timer/event counter 1 reloading will occur at the same time). When the timer/event counter 1 (reading TMR1) is read, the clock will be blocked to avoid errors. As this may results in a counting error, this must be taken into consideration by the programmer. The bit 0~2 of the TMR1C can be used to define the pre-scaling stages of the internal clock sources of timer/event counter 1. The definitions are as shown. fS fR YS TC M U fS 1 X 8 - s ta g e P r e s c a le r 8 -1 M U X f IN T1 D a ta B u s T1M 1 T1M 0 T1E T im e r /E v e n t C o u n te r 1 P r e lo a d R e g is te r R e lo a d T1S PS1C2~PS1C0 TM R1 T1M 1 T1M 0 T1O N P u ls e W id th M e a s u re m e n t M o d e C o n tro l T im e r /E v e n t C o u n te r (T M R 1 ) 2 O v e r flo w to In te rru p t PFD Timer/Event Counter 1 Bit No. Label Function Define the prescaler stages, P1SC2, P1SC1, P1SC0= 000: fINT1=fS1/2 001: fINT1=fS1/4 010: fINT1=fS1/8 011: fINT1=fS1/16 100: fINT1=fS1/32 101: fINT1=fS1/64 110: fINT1=fS1/128 111: fINT1=fS1/256 Defines the TMR1 active edge of the timer/event counter: In Event Counter Mode (T1M1,T1M0)=(0,1): 1:count on falling edge; 0:count on rising edge In Pulse Width measurement mode (T1M1,T1M0)=(1,1): 1: start counting on the rising edge, stop on the falling edge; 0: start counting on the falling edge, stop on the rising edge To enable or disable timer 1 counting (0=disable; 1=enable) Select clock source of TMR1 (0=fSYS; 1=fRTC) Define the operating mode, T1M1, T1M0= 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMR1C (11H) Register 0 1 2 P1SC0 P1SC1 P1SC2 3 T1E 4 5 T1ON T1S 6 7 T1M0 T1M1 Rev. 1.00 16 July 27, 2007 HT48R54A Input/Output Ports There are 16 bidirectional input/output (PA, PB) lines and 8 PMOS (PC), 16 NMOS (PD, PE) output lines in the microcontroller, labeled from PA to PE, which are mapped to the data memory of [12H], [14H], [16H], [18H] and [1AH] respectively. All pins on PA~PB can be used for both input and output operations. For the input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction MOV A,[m] (m=12H, 14H). For output operation, all the data is latched and remains unchanged until the output latch is rewritten. The PA and PB have their own control registers (PAC, PBC) to control the input/output configuration. These two control registers are mapped to locations 13H and 15H. CMOS/PMOS output or Schmitt trigger input with structures can be reconfigured dynamically under software control. The control registers specifies which pin are set as input and which are set as outputs. To setup a pin as an input the corresponding bit of the control register must be set high, for an output it must be set low. The PC can be used for output operation only. Resetting its output register to low will effectively places its PMOS output transistor in high impedance state. Setting output register to high will force PC to output high state. The external interrupt pin INT is pin-shard with output pin PD0. The PD and PE can be used for output operation only. Setting its output register high which effectively places its NMOS output transistor in high impedance state. Resetting output register to low will force to output low state. After a chip reset, these input/output lines remain at high levels or floating state (depending on the pull-high options). Each bit of these input/output latches can be set or cleared by SET [m].i and CLR [m].i (m=12H, 14H, 16H, 18H or 1AH) instructions. Some instructions first input data and then follow the output operations. For example, SET [m].i, LR [m].i, CPL [m], CPLA [m] read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. Each line of port A has the capability of waking-up the device. There is a pull-high option available for PA0~PA7 lines (port option). Once the pull-high option of an I/O line is selected, the I/O line have pull-high resistor. Otherwise, the pull-high resistor is absent. It should be noted that a non-pull-high I/O line operating in input mode will cause a floating state. V DD D a ta B u s W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r C o n tr o l B it Q D CK S Q P u ll- H ig h O p tio n D a ta B it Q D CK S Q M U X W r ite D a ta R e g is te r PA PA PA PA PA PA 0 /B 1 /B 2 /T 3 /T 4~ 7 /P MR0 MR1 PA6 FD Z Z PA7 orPA0 P F D o r B Z /B Z M U X R e a d D a ta R e g is te r S y s te m W a k e -u p BZ orPFD O p tio n W a k e - u p O p tio n T M R 0 fo r P A 2 o n ly T M R 1 fo r P A 3 o n ly PA Input/Output Ports Rev. 1.00 17 July 27, 2007 HT48R54A C o n tr o l B it Q D CK S Q V DD D a ta B u s W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r D a ta B it D Q CK S Q M U X PB0~PB7 W r ite D a ta R e g is te r R e a d D a ta R e g is te r PB Input/Output Ports V D a ta B it DD D a ta B u s W r ite D a ta R e g is te r C h ip R e s e t R e a d D a ta R e g is te r D CK R Q Q PC 0~PC 7 PC Output Ports D a ta B it P D 0 /IN T D a ta B u s W r ite D a ta R e g is te r C h ip R e s e t R e a d D a ta R e g is te r IN T In p u t D CK S Q Q PD0 Input/Output Port D a ta B it D a ta B u s D CK S Q W r ite D a ta R e g is te r C h ip R e s e t R e a d D a ta R e g is te r Q PD 1~PD 7 PE0~PE7 PD1~PD7, PE Output Ports Rev. 1.00 18 July 27, 2007 HT48R54A Buzzer Output The PA0 and PA1 are pin-shared with BZ and BZ signal, respectively. If the BZ/BZ option is selected, the output signal in output mode of PA0/PA1 will be the buzzer signal generated by Multi-function timer. The input mode is always remained in its original functions. Once the BZ/BZ option is selected, the buzzer output signals are controlled by the PA0 data register only. The I/O functions of PA0/PA1 are shown below. PAC Register PAC0 0 0 0 0 1 1 Note: PAC Register PAC1 0 0 1 1 0 1 PA Data Register PA0 1 0 1 0 x x PA Data Register PA1 x x x x D x Output Function PA0=BZ, PA1=BZ PA0=0, PA1=0 PA0=BZ, PA1=input PA0=0, PA1=input PA0=input, PA1=0 PA0=input, PA1=input x stands for dont care D stands for Data 0 or 1 PFD Output The PA7 is pin-shared with the PFD signal. If the PFD option is selected, the output signal in output mode of PA7 will be the PFD signal generated by timer/event counter 1 overflow signal. The input mode is always remaining its original functions. Once the PFD option is selected, the PFD output signal is controlled by PA7 data register only. The I/O functions of PA7 are shown below. I/O Mode PA7 Note: I/P (Normal) Logical Input O/P (Normal) Logical Output I/P (PFD) Logical Input O/P (PFD) PFD (Timer on) The PFD frequency is the timer/event counter 1 overflow frequency divided by 2. The definitions of the PFD control signal and PFD output frequency are listed in the following table. Timer OFF OFF ON ON Note: Timer Preload Value X X N N PA7 Data Register 0 1 0 1 PA7 Pad State 0 U 0 PFD PFD Frequency X X X fTMR1/[2(M-N)] X stands for unused U stands for unknown M is 65536 for PFD N is the preload value for the timer/event counter 1 fTMR1 is input clock frequency for timer/event counter 1 Rev. 1.00 19 July 27, 2007 HT48R54A Low Voltage Reset - LVR The microcontroller provides a low voltage reset circuit in order to monitor the supply voltage of the device. If the supply voltage of the device is within the range 0.9V~VLVR, such as changing a battery, the LVR will automatically reset the device internally. The LVR includes the following specifications: * The low voltage (0.9V~VLVR) has to remain in their original state for more than 1ms. If the low voltage state does not exceed 1ms, the LVR will ignore it and do not perform a reset function. * The LVR uses the OR function with the external RES signal to perform a chip reset. The relationship between VDD and VLVR is shown below. VDD 5 .5 V V OPR 5 .5 V VDD 5 .5 V V OPR 5 .5 V VDD 5 .5 V V OPR 5 .5 V V 2 .1 V 2 .2 V LVR V 3 .1 5 V 2 .2 V LVR V 4 .2 V 2 .2 V LVR 0 .9 V 0 .9 V 0 .9 V Note: VOPR is the voltage range for proper chip operation at 4MHz system clock. V 5 .5 V DD V LVR LVR D e te c t V o lta g e 0 .9 V 0V R e s e t S ig n a l R eset *1 N o r m a l O p e r a tio n *2 R eset Low Voltage Reset Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system clock pulses before entering the normal operation. *2: Since a low voltage has to be maintained for more than 1ms, therefore a 1ms delay is provided before entering the reset mode. Rev. 1.00 20 July 27, 2007 HT48R54A Options The following table shows all kinds of options in the microcontroller. All of the options must be defined to ensure having a proper functioning system. Items 1 2 3 4 5 6 7 8 9 10 11 12 OSC type selection: RC or crystal PA0~PA7 bit wake-up enable or disable (by bit) PA pull-high enable or disable (by port) WDT clock source: WDT oscillator or fSYS/4 or 32768Hz oscillator WDT enable or disable CLRWDT instructions: 1 or 2 instructions Timer/event counter 0 clock sources: fSYS/4 or fSP LVR enable or disable LVR voltage: 2.1V or 3.15V or 4.2V Buzzer function: single BZ enable or both BZ and BZ or both disable Buzzer frequency: fS/2, fS/4, fS/8, fS/16 PA7: Normal I/O or PFD output Options Rev. 1.00 21 July 27, 2007 HT48R54A Application Circuits V DD VDD Reset C ir c u it RES 0 .1 m F VSS PA PA P P 100kW 0 .1 m F PA0 PA1 2 /T M 3 /T M A4~P A 7 /P /B /B R R Z Z 1 0 A6 FD PB0~PB7 V PC 0~PC 7 P D 0 /IN T PD 1~PD 7 DD 470pF R OSC OSC1 fS YS R C S y s te m 130kW O s c illa to r < 2 .4 M W /4 OSC2 OSC1 OSC C ir c u it 32768H z 10pF OSC1 OSC2 OSC3 PE0~PE7 C1 R1 C2 C r y s ta l/R e s o n a to r S y s te m O s c illa to r F o r R 1 , C 1 , C 2 s e e n o te OSC2 OSC4 H T48R 54A OSC C ir c u it Note: 1. Crystal/resonator system oscillators For crystal oscillators, C1 and C2 are only required for some crystal frequencies to ensure oscillation. For resonator applications C1 and C2 are normally required for oscillation to occur. For most applications it is not necessary to add R1. However if the LVR function is disabled, and if it is required to stop the oscillator when VDD falls below its operating range, it is recommended that R1 is added. The values of C1 and C2 should be selected in consultation with the crystal/resonator manufacturer specifications. 2. Reset circuit The reset circuit resistance and capacitance values should be chosen to ensure that VDD is stable and remains within its operating voltage range before the RES pin reaches a high level. Ensure that the length of the wiring connected to the RES pin is kept as short as possible, to avoid noise interference. 3. For applications where noise may interfere with the reset circuit and for details on the oscillator external components, refer to Application Note HA0075E for more information. Rev. 1.00 22 July 27, 2007 HT48R54A Instruction Set Summary Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Add data memory to ACC Add ACC to data memory Add immediate data to ACC Add data memory to ACC with carry Add ACC to data memory with carry Subtract immediate data from ACC Subtract data memory from ACC Subtract data memory from ACC with result in data memory Subtract data memory from ACC with carry Subtract data memory from ACC with carry and result in data memory Decimal adjust ACC for addition with result in data memory 1 1(1) 1 1 1(1) 1 1 1(1) 1 1(1) 1(1) Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV C Description Instruction Cycle Flag Affected Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC Complement data memory Complement data memory with result in ACC 1 1 1 1(1) 1(1) 1(1) 1 1 1 1(1) 1 Z Z Z Z Z Z Z Z Z Z Z Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Clear bit of data memory Set bit of data memory 1(1) 1(1) None None Move data memory to ACC Move ACC to data memory Move immediate data to ACC 1 1(1) 1 None None None Rotate data memory right with result in ACC Rotate data memory right Rotate data memory right through carry with result in ACC Rotate data memory right through carry Rotate data memory left with result in ACC Rotate data memory left Rotate data memory left through carry with result in ACC Rotate data memory left through carry 1 1(1) 1 1(1) 1 1(1) 1 1(1) None None C C None None C C Increment data memory with result in ACC Increment data memory Decrement data memory with result in ACC Decrement data memory 1 1(1) 1 1(1) Z Z Z Z Rev. 1.00 23 July 27, 2007 HT48R54A Mnemonic Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: No operation Clear data memory Set data memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of data memory Swap nibbles of data memory with result in ACC Enter power down mode 1 1(1) 1(1) 1 1 1 1(1) 1 1 None None None TO,PDF TO(4),PDF(4) TO(4),PDF(4) None None TO,PDF Read ROM code (current page) to data memory and TBLH Read ROM code (last page) to data memory and TBLH 2(1) 2(1) None None Jump unconditionally Skip if data memory is zero Skip if data memory is zero with data movement to ACC Skip if bit i of data memory is zero Skip if bit i of data memory is not zero Skip if increment data memory is zero Skip if decrement data memory is zero Skip if increment data memory is zero with result in ACC Skip if decrement data memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1(2) 1(2) 1(2) 1(2) 1(3) 1(3) 1(2) 1(2) 2 2 2 2 None None None None None None None None None None None None None Description Instruction Cycle Flag Affected x: Immediate data m: Data memory address A: Accumulator i: 0~7 number of bits addr: Program memory address O: Flag is affected -: Flag is not affected (1) : If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). : If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). Otherwise the original instruction cycle is unchanged. : and (2) : The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged. (2) (3) (1) (4) Rev. 1.00 24 July 27, 2007 HT48R54A Instruction Definition ADC A,[m] Description Operation Affected flag(s) TO 3/4 ADCM A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,x Description Operation Affected flag(s) TO 3/4 ADDM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Add data memory and carry to the accumulator The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator. ACC ACC+[m]+C Add the accumulator and carry to data memory The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory. [m] ACC+[m]+C Add data memory to the accumulator The contents of the specified data memory and the accumulator are added. The result is stored in the accumulator. ACC ACC+[m] Add immediate data to the accumulator The contents of the accumulator and the specified data are added, leaving the result in the accumulator. ACC ACC+x Add the accumulator to the data memory The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. [m] ACC+[m] Rev. 1.00 25 July 27, 2007 HT48R54A AND A,[m] Description Operation Affected flag(s) TO 3/4 AND A,x Description Operation Affected flag(s) TO 3/4 ANDM A,[m] Description Operation Affected flag(s) TO 3/4 CALL addr Description PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical AND accumulator with data memory Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND [m] Logical AND immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND x Logical AND data memory with the accumulator Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory. [m] ACC AND [m] Subroutine call The instruction unconditionally calls a subroutine located at the indicated address. The program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. The indicated address is then loaded. Program execution continues with the instruction at this address. Stack Program Counter+1 Program Counter addr Operation Affected flag(s) TO 3/4 CLR [m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Clear data memory The contents of the specified data memory are cleared to 0. [m] 00H PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Rev. 1.00 26 July 27, 2007 HT48R54A CLR [m].i Description Operation Affected flag(s) TO 3/4 CLR WDT Description Operation Affected flag(s) TO 0 CLR WDT1 Description PDF 0 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Clear bit of data memory The bit i of the specified data memory is cleared to 0. [m].i 0 Clear Watchdog Timer The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are cleared. WDT 00H PDF and TO 0 Preclear Watchdog Timer Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0* Operation Affected flag(s) TO 0* CLR WDT2 Description PDF 0* OV 3/4 Z 3/4 AC 3/4 C 3/4 Preclear Watchdog Timer Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0* Operation Affected flag(s) TO 0* CPL [m] Description Operation Affected flag(s) TO 3/4 PDF 0* OV 3/4 Z 3/4 AC 3/4 C 3/4 Complement data memory Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. [m] [m] PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Rev. 1.00 27 July 27, 2007 HT48R54A CPLA [m] Description Complement data memory and place result in the accumulator Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remain unchanged. ACC [m] Operation Affected flag(s) TO 3/4 DAA [m] Description PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Decimal-Adjust accumulator for addition The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored in the data memory and only the carry flag (C) may be affected. If ACC.3~ACC.0 >9 or AC=1 then [m].3~[m].0 (ACC.3~ACC.0)+6, AC1=AC else [m].3~[m].0 (ACC.3~ACC.0), AC1=0 and If ACC.7~ACC.4+AC1 >9 or C=1 then [m].7~[m].4 ACC.7~ACC.4+6+AC1,C=1 else [m].7~[m].4 ACC.7~ACC.4+AC1,C=C Operation Affected flag(s) TO 3/4 DEC [m] Description Operation Affected flag(s) TO 3/4 DECA [m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O Decrement data memory Data in the specified data memory is decremented by 1. [m] [m]-1 Decrement data memory and place result in the accumulator Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]-1 Rev. 1.00 28 July 27, 2007 HT48R54A HALT Description Enter power down mode This instruction stops program execution and turns off the system clock. The contents of the RAM and registers are retained. The WDT and prescaler are cleared. The power down bit (PDF) is set and the WDT time-out bit (TO) is cleared. Program Counter Program Counter+1 PDF 1 TO 0 Operation Affected flag(s) TO 0 INC [m] Description Operation Affected flag(s) TO 3/4 INCA [m] Description Operation Affected flag(s) TO 3/4 JMP addr Description Operation Affected flag(s) TO 3/4 MOV A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Directly jump The program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. Program Counter addr PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 1 OV 3/4 Z 3/4 AC 3/4 C 3/4 Increment data memory Data in the specified data memory is incremented by 1 [m] [m]+1 Increment data memory and place result in the accumulator Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]+1 Move data memory to the accumulator The contents of the specified data memory are copied to the accumulator. ACC [m] Rev. 1.00 29 July 27, 2007 HT48R54A MOV A,x Description Operation Affected flag(s) TO 3/4 MOV [m],A Description Operation Affected flag(s) TO 3/4 NOP Description Operation Affected flag(s) TO 3/4 OR A,[m] Description Operation Affected flag(s) TO 3/4 OR A,x Description Operation Affected flag(s) TO 3/4 ORM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 No operation No operation is performed. Execution continues with the next instruction. Program Counter Program Counter+1 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Move immediate data to the accumulator The 8-bit data specified by the code is loaded into the accumulator. ACC x Move the accumulator to data memory The contents of the accumulator are copied to the specified data memory (one of the data memories). [m] ACC Logical OR accumulator with data memory Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR [m] Logical OR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR x Logical OR data memory with the accumulator Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. [m] ACC OR [m] Rev. 1.00 30 July 27, 2007 HT48R54A RET Description Operation Affected flag(s) TO 3/4 RET A,x Description Operation Affected flag(s) TO 3/4 RETI Description Operation Affected flag(s) TO 3/4 RL [m] Description Operation Affected flag(s) TO 3/4 RLA [m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Return from subroutine The program counter is restored from the stack. This is a 2-cycle instruction. Program Counter Stack Return and place immediate data in the accumulator The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data. Program Counter Stack ACC x Return from interrupt The program counter is restored from the stack, and interrupts are enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit. Program Counter Stack EMI 1 Rotate data memory left The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7 Rotate data memory left and place result in the accumulator Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7 Rev. 1.00 31 July 27, 2007 HT48R54A RLC [m] Description Operation Rotate data memory left through carry The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 C C [m].7 Affected flag(s) TO 3/4 RLCA [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O Rotate left through carry and place result in the accumulator Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored in the accumulator but the contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 C C [m].7 Operation Affected flag(s) TO 3/4 RR [m] Description Operation Affected flag(s) TO 3/4 RRA [m] Description Operation Affected flag(s) TO 3/4 RRC [m] Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O Rotate data memory right The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0 Rotate right and place result in the accumulator Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 [m].0 Rotate data memory right through carry The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 C C [m].0 Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O Rev. 1.00 32 July 27, 2007 HT48R54A RRCA [m] Description Rotate right through carry and place result in the accumulator Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is stored in the accumulator. The contents of the data memory remain unchanged. ACC.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 C C [m].0 Operation Affected flag(s) TO 3/4 SBC A,[m] Description Operation Affected flag(s) TO 3/4 SBCM A,[m] Description Operation Affected flag(s) TO 3/4 SDZ [m] Description PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator. ACC ACC+[m]+C Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory. [m] ACC+[m]+C Skip if decrement data memory is 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, [m] ([m]-1) Operation Affected flag(s) TO 3/4 SDZA [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Decrement data memory and place result in ACC, skip if 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, ACC ([m]-1) Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Rev. 1.00 33 July 27, 2007 HT48R54A SET [m] Description Operation Affected flag(s) TO 3/4 SET [m]. i Description Operation Affected flag(s) TO 3/4 SIZ [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Set data memory Each bit of the specified data memory is set to 1. [m] FFH Set bit of data memory Bit i of the specified data memory is set to 1. [m].i 1 Skip if increment data memory is 0 The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, [m] ([m]+1) Operation Affected flag(s) TO 3/4 SIZA [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Increment data memory and place result in ACC, skip if 0 The contents of the specified data memory are incremented by 1. If the result is 0, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, ACC ([m]+1) Operation Affected flag(s) TO 3/4 SNZ [m].i Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Skip if bit i of the data memory is not 0 If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i0 Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Rev. 1.00 34 July 27, 2007 HT48R54A SUB A,[m] Description Operation Affected flag(s) TO 3/4 SUBM A,[m] Description Operation Affected flag(s) TO 3/4 SUB A,x Description Operation Affected flag(s) TO 3/4 SWAP [m] Description Operation Affected flag(s) TO 3/4 SWAPA [m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+[m]+1 Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. [m] ACC+[m]+1 Subtract immediate data from the accumulator The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+x+1 Swap nibbles within the data memory The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged. [m].3~[m].0 [m].7~[m].4 Swap data memory and place result in the accumulator The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged. ACC.3~ACC.0 [m].7~[m].4 ACC.7~ACC.4 [m].3~[m].0 Rev. 1.00 35 July 27, 2007 HT48R54A SZ [m] Description Skip if data memory is 0 If the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0 Operation Affected flag(s) TO 3/4 SZA [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Move data memory to ACC, skip if 0 The contents of the specified data memory are copied to the accumulator. If the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0 Operation Affected flag(s) TO 3/4 SZ [m].i Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Skip if bit i of the data memory is 0 If bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i=0 Operation Affected flag(s) TO 3/4 TABRDC [m] Description Operation Affected flag(s) TO 3/4 TABRDL [m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Move the ROM code (current page) to TBLH and data memory The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte) PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Move the ROM code (last page) to TBLH and data memory The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte) PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Rev. 1.00 36 July 27, 2007 HT48R54A XOR A,[m] Description Operation Affected flag(s) TO 3/4 XORM A,[m] Description Operation Affected flag(s) TO 3/4 XOR A,x Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical XOR accumulator with data memory Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator. ACC ACC XOR [m] Logical XOR data memory with the accumulator Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected. [m] ACC XOR [m] Logical XOR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected. ACC ACC XOR x Rev. 1.00 37 July 27, 2007 HT48R54A Package Information 44-pin QFP (1010) Outline Dimensions C D G 23 I 34 22 L F A B E 44 12 K 1 11 a J 33 H Symbol A B C D E F G H I J K L a Dimensions in mm Min. 13 9.9 13 9.9 3/4 3/4 1.9 3/4 0.25 0.73 0.1 3/4 0 Nom. 3/4 3/4 3/4 3/4 0.8 0.3 3/4 3/4 3/4 3/4 3/4 0.1 3/4 Max. 13.4 10.1 13.4 10.1 3/4 3/4 2.2 2.7 0.5 0.93 0.2 3/4 7 Rev. 1.00 38 July 27, 2007 HT48R54A 52-pin QFP (1414) Outline Dimensions C D 39 27 G H I 40 26 F A B E 52 14 K J 1 13 Symbol A B C D E F G H I J K a Dimensions in mm Min. 17.3 13.9 17.3 13.9 3/4 3/4 2.5 3/4 3/4 0.73 0.1 0 Nom. 3/4 3/4 3/4 3/4 1 0.4 3/4 3/4 0.1 3/4 3/4 3/4 Max. 17.5 14.1 17.5 14.1 3/4 3/4 3.1 3.4 3/4 1.03 0.2 7 Rev. 1.00 39 July 27, 2007 HT48R54A Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 86-21-6485-5560 Fax: 86-21-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 Fax: 86-10-6641-0125 Holtek Semiconductor Inc. (Chengdu Sales Office) 709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016 Tel: 86-28-6653-6590 Fax: 86-28-6653-6591 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com Copyright O 2007 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 40 July 27, 2007 |
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